1. Field of the Invention
The present invention relates to a charge coupled device, and more particularly to a bidirectional horizontal charge transfer device for a mirror image sensor which allows bidirectional transfer of a signal charge.
2. Description of the Prior Art
Generally, a horizontal charge transfer channel requires a rapid clocking to sense the charge transmitted in parallel from a vertical charge transfer channel within a short time period.
For this reason, the horizontal charge transfer channel typically adopts a 2-phase clocking, which is different from the clocking used in a vertical charge transfer channel.
A conventional horizontal charge coupled device (hereinafter referred to as "HCCD") will be described below with reference to the accompanying drawings.
FIG. 1A is a sectional view showing a structure of a conventional HCCD, FIG. 1B shows a potential profile of the conventional HCCD, and FIG. 1C shows clock signals applied to poly gates of the conventional HCCD.
The conventional HCCD includes a P-type well formed in an N-type semiconductor substrate, and a BCCD 1 formed on a predetermined portion of the P-type well to function as a horizontal charge transfer channel. A gate insulating layer 3 is formed on the BCCD 1 over the surface of the N-type semiconductor substrate. First and second poly gates 4a and 4b are alternatively formed over the gate insulating layer 3 while being insulated from each other. In addition, barrier rcgionu 2 which are supplied with a clock signal H01 or H02 underlie one of the first and second poly gates 4a and 4b.
The conventional HCCD constructed as above, as shown in FIG. 1B, forms a step-type potential well to transmit the charge in one direction even though a same clock signal is applied through the barrier regions 2.
Referring to FIGS. 1B and 1C, since the bottom of the potential well is in the low energy level state, electrons are gathered thereto. That is, electrons are gathered to the potential well under the fourth poly gate 4', which is supplied with the high level clock signal H02 when t=1.
When t=2, a high voltage is applied to the first and second poly gates 1' and 2' so as to lower the energy level of the lower portions of the first and second poly gates 1' and 2', and a low voltage is applied to the third and fourth poly gates 3' and 4' so as to raise the energy level of the third and fourth poly gates 3' and 4'.
However, the electrons gathered around the lower potential well of the fourth poly gate 4' cannot migrate left due to the barrier region 2 under the third poly gate 3'.
If the energy level of the fifth and sixth poly gates 5' and 6' were to be lowered gradually to remove the barrier region on the right of the fourth poly gate 4', the electrons would migrate to the lower portions of the fifth and sixth poly gates 5' and 6' having the low energy level.
Then, when the bias of the fifth and sixth poly gates 5' and 6' is sufficiently raised, the step-type potential well is formed again to move the gathered electrons from the lower portion of the fourth poly gate 4' to the lower portion of sixth poly gate 6'.
In case that t=3, the first, second, fifth and sixth poly gates 1', 2', 5' and 6' are supplied with the low voltage while the third, fourth, seventh and eighth poly gates 3', 4', 7' and 8' are supplied with the high voltage so as to have the same result as when t=0.
A period of the clock signal is from L=1 to t=3. During a one clock signal period, the electrons migrate from the lower portion of the fourth poly gate 4' to the lower portion of the eighth poly gate 8'.
The conventional HCCD using the 2-phase clocking of signals H01 and H02, however, is disadvantageous, for example, in that the barrier layer is formed below one of the first and second poly gates such that a charge can migrate only in one direction.
Therefore, the conventional HCCD cannot be utilized in a mirror image censor which requires a bidirectional charge transfer.